This page describes how to run coreboot on the Facebook Monolith.
Please note: the coreboot implementation for this board is in its Beta state and isn’t fully tested yet.
|FSP Project Name||Directory||Specification|
|7th Generation Intel® Core™ processors and chipsets (formerly Kaby Lake)||KabylakeFspBinPkg||2.0|
To create a complete flash image, the flash descriptor, GBE and ME blobs are required. The complete image can be used when e.g. a blank flash should be programmed. In other cases (when only coreboot needs to be replaced) placeholders can be used for the GBE and ME regions.
These can be extracted from the original flash image as follows:
- Read the complete image from flash.
- Create a layout file with the following content:
00000000:00000fff fd 00700000:00ffffff bios 00003000:006FFFFF me 00001000:00002fff gbe
ifdtool -n <layout_file> <flash_image>to resize the bios region from the default 6 MiB to 9 MiB, this is required to create sufficient space for LinuxBoot. NOTE: Please make sure only the firmware descriptor (fd) region is changed. Older versions of the ifdtool corrupt the me region.
ifdtool -x <resized_flash_image>to extract the components.
The regions extracted can be used to generate a full flash image. The bios region is not needed as this is replaced by the coreboot image.
NOTE: The gbe region contains the MAC address so be careful. When updating the flash using flashrom it is advisable to leave out the gbe area.
The SPI flash can be accessed using flashrom.
The descriptor area needs to be updated once to resize the bios region.
flashrom -p internal --ifd -i fd -w <coreboot.bin>
After that only the bios area should to be updated.
flashrom -p internal --ifd -i bios -w <coreboot.bin>
The gbe and me regions should not be updated.
flashrom --ifd uses the flash descriptor it is required to update the
descriptor and bios regions in the right sequence. Don’t update both in one command.
The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip. Specifically, it’s a Winbond W25Q128JVSIQ (3.3V).
The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip. Specifically, it’s a Winbond W25Q128JVSIM (3.3V).
Flashing of these devices is very difficult, disassembling the system destroys the cooling solution. Wires need to be connected to be able to flash using an external programmer.
- Hardware monitor
- Full Embedded Controller support
- Gigabit Ethernet (i219 and i210)
- Graphics (Using FSP GOP)
- PCIe including hotplug on FPGA root port
- EC serial port
- EC CPU temperature
- Initialization with FSP
- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
- LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload and LinuxBoot.
SeaBios has been checked to the extend that it runs to the boot selection and provides display output.
|SoC||Intel Kaby Lake U|
|Super I/O, EC||ITE8528|
|Coprocessor||Intel Management Engine|