Firmware and Computer Acronyms, Initialisms and Definitions¶
** Note that this document even more of a work in progress than most ** ** of the coreboot documentation **
- _XXX - An underscore followed by 3 uppercase letters will typically be
an ACPI specified method. Look in the ACPI
Spec for details, or run the tool
- 2FA - Two-factor Authentication
- 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space. Better abbreviated as 4GiB
- 5G - Telecommunication: Fifth-Generation Cellular Network
ABL - AMD: AGESA BootLoader (or AMD BootLoader) - The portion of the AMD processor initialization that happens from the PSP. Significantly, Memory Initialization.
AC - Electricity: Alternating Current
Ack - Acknowledgment
ACP - Average CPU power
ACPI - The Advanced Configuration and Power Interface is an industry standard for letting the OS control power management.
ADL - Intel: Alder Lake
AGP - The Accelerated Graphics Port is an older (1997-2004) point-to-point bus for video cards to communicate with the processor.
AHCI - The Advanced Host Controller Interface is a standard register set for communicating with a SATA controller.
AIC - Add-in Card
AIO - Computer formfactor: All In One
ALIB - AMD: ACPI-ASL Library
ALS - Ambient Light Sensor
ALU - Arithmetic Logic Unit
AMBA - ARM: Advanced Microcontroller Bus Architecture: An open standard to connect and manage functional blocks in an SoC (System on a Chip)
AMD64 - Another name for x86-64
AMPL - AMD: Advanced Platform Management Link - Also referred to as SBI: Sideband Interface
AMT - Intel: Active Management Technology
AOAC - AMD: Always On, Always Connected
AP - Application processor - The main processor on the board (as opposed to the embedded controller or other processors that may be on the system), any cores in the processor chip that aren’t the BSP (Boot Strap Processor).
APCB - AMD: AMD PSP Customization Block
APIC - Advanced Programmable Interrupt Controller this is an advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
APL - Intel: Apollo Lake
APM - Advanced Power Management - The standard for power management before ACPI (Yes, they’re both advanced). APM was managed entirely by the firmware and the operating system had no control or even awareness of the power management.
APOB - AMD: AGESA PSP Output Buffer
APU - AMD: Accelerated Processing Unit
ARC - HDMI: Audio Return Channel
ARM - Advanced RISC Machines - Originally Acorn RISC Machine. This may refer to either the company or the instruction set.
ARP - Networking: Address Resolution Protocol
ASEG - The A_0000h-B_FFFFh memory segment - this area was typically hidden by the Video BIOS
ASF - Alert Standard Format
ASL - ACPI Source Language
ASLR - Address Space Layout Randomization
ASP - AMD: AMD Security Processor (Formerly the PSP - Platform Security Processor)
ASPM - PCI: Active State Power Management
ATS - PCIe: Address Translation Services
ATAPI - ATA Packet Interface
- BAR - Base Address Register This generally refers to one of the base address registers in the PCI config space of a PCI device
- Baud - Baud - Not an acronym - Symbol rate unit of symbols per second, named after Émile Baudot
- BBS - BIOS boot specification
- BCD - Binary-Coded Decimal
- BCT - Intel: Binary Configuration Tool
- BDA - BIOS Data Area This refers to the memory area of 0x40:0000 which is where the original PC-BIOS stored its data tables.
- BDF - BUS, Device, Function - A way of referencing a PCI Device function address.
- BDS - UEFI: Boot-Device Select
- BDW - Intel: Broadwell
- BERT - ACPI: Boot Error Record Table
- BGA - Ball Grid Array
- BGP - Networking: Border Gateway Protocol
- Big Real mode - Real mode running in a way that allows it to access the entire 4GiB of the 32-bit address space. Also known as flat mode or Unreal mode.
- BIOS - Basic Input/Output System
- BIST - The Built-in Self Test is a test run by the processor on itself when it is first started. Usually, any nonzero value indicates that the selftest failed.
- Bit-banging - Bit-banging - A term for the method of emulating a more complex protocol by using GPIOs.
- BKDG - AMD: Bios & Kernel Developers’ guide (Replaced by the PPR - Processor Programming Reference)
- BLOB - Binary Large OBject - Originally a collection of binary files stored as a single object, this was co-opted by the open source communities to mean any proprietary binary file that is not available as source code.
- BM - Bus Master
- BMC - Baseboard Management Controller
- BMP - Bitmap
- BOM - Bill of Materials
- BPDT - Boot Partition Description Table
- bps - Bits Per Second
- BS - coreboot: Boot State - coreboot’s ramstage sequence are made up of boot states. Each of these states can be hooked to run functions before the stat, during the state, or after the state is complete.
- BSF - Intel: Boot Specification File
- BSP - BootStrap Processor - The initialization core of the main system processor. This is the processor core that starts the boot process.
- BSS - Block Starting Symbol
- BT - Bluetooth
- Bus - Initially a term for a number of connectors wired together in parallel, this is now used as a term for any hardware communication method.
- BWG - Intel: BIOS Writers Guide
- C-states: ACPI Processor Idle states. C-States C0-Cx: Each higher number saves more power, but takes longer to return to a fully running processor.
- C0 - ACPI Defined Processor Idle state: Active - CPU is running
- C1 - ACPI Defined Processor Idle state: Halt - Nothing currently running, but can start running again immediately
- C2 - ACPI Defined Processor Idle state: Stop-clock - core clocks off
- C3 - ACPI Defined Processor Idle state: Sleep - L1 & L2 caches may be saved to Last Level Cache (LLC), core powered down.
- C4+ - Processor Specific idle states
- CAR - Cache As RAM
- CBFS - coreboot filesystem
- CBMEM - coreboot Memory
- CBI - Google: CrOS Board Information
- CDN - Content Delivery Network
- CEM - PCIe: Card ElectroMechanical specification
- CFL - Coffee Lake
- CID - Coverity ID
- CIM - Common Information Model
- CISC - Complex Instruction Set Computer
- CL - ChangeList - Another name for a patch or commit. This seems to be Perforce notation.
- CLK - Clock - Used when there isn’t enough room for 2 additional characters - similar to RST, for people who hate vowels.
- CML - Intel: Comet Lake
- CMOS - Complementary Metal Oxide
- This is a method of making ICs (Integrated Circuits). For BIOS, it’s generally used to describe a section of NVRAM (Non-volatile RAM), in this case a section battery-backed memory in the RTC (Real Time Clock) that is typically used to store BIOS settings. *http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory
- CNL - Intel: Cannon Lake (formerly Skymont)
- CNVi - Intel: Connectivity Integration
- CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
- CPLD - Complex Programmable Logic Device
- CPPC - AMD: Collaborative Processor Performance Controls
- CPS - Characters Per Second
- CPU - Central Processing Unit
- CPUID - x86: CPU Identification opcode
- Cr50 - Google: The first generation Google Security Chip (GSC) used on ChromeOS devices.
- CRB - Customer Reference Board
- CRLF - Carriage Return, Line Feed - \r\n - The standard window EOL (End-of-Line) marker.
- crt0 - C Run Time 0
- crt0s - crt0 Source code
- CRT - Cathode Ray Tube
- CSE - Intel: Converged Security Engine
- CSI - MIPI: Camera Serial Interface
- CSME - Intel: Converged Security and Management Engine
- CTLE - Intel: Continuous Time Linear Equalization
- CVE - Common Vulnerabilities and Exposures
- CZN - AMD: Cezanne - CPU Family 19h, Model 50h
- D$ - Data Cache
- D-States - ACPI Device power states D0-D3 - These are device specific power states, with each higher number requiring less power, and typically taking a longer time to get back to D0, fully running.
- D0 - ACPI Device power state: Active - Device fully on and running
- D1 - ACPI Device power state: Lower power than D0
- D2 - ACPI Device power state: Lower power than D1
- D3 Hot - ACPI Device power state: Device is in a low power state, but still has power.
- D3 Cold - ACPI Device power state: Power is completely removed from the device.
- DASH - Desktop and mobile Architecture for System Hardware
- DB - DaughterBoard
- DC - Electricity: Direct Current
- DCP - Digital Content Protection
- DCR - Decode Control Register This is a way of identifying the hardware in question. This is generally paired with a Vendor ID (VID)
- DDC - Display Data Channel
- DDI - Intel: Digital Display Interface
- DDR - Double Data Rate
- DEVAPC - Mediatek: Device Access Permission Control
- DF - Data Fabric
- DFP - USB: Downstream Facing port
- DHCP - Dynamic Host Configuration Protocol
- DID - Device Identifier
- DIMM - Dual Inline Memory Module
- DIP - Dual inline package
- DMA - Direct Memory Access Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
- DMI - Direct Media Interface is a link/bus between CPU and PCH.
- DMI - Desktop Management Interface
- DMIC - Digital Microphone
- DMTF - Distributed Management Task Force
- DMZ - Demilitarized Zone
- DNS - Domain Name Service
- DNV - Intel: Denverton
- DOS - Disk Operating System
- DP - DisplayPort
- DPM - Mediatek: DRAM Power Manager
- DPTF - Intel: Dynamic Power and Thermal Framework
- DRAM - Memory: Dynamic Random Access Memory
- DRTM - Dynamic Root of Trust for Measurement
- DQ - Memory: Data I/O signals. On a D-flipflop, used for SRAM, the data-in pin is generally referred to as D, and the data-out pin is Q, thus the IO Data signal lines are referred to as DQ lines.
- DQS - Memory: Data Q Strobe - Data valid signal for DDR memory.
- DRM - Digital Rights Management
- DRP - USB: Port than can be switched between either a Downstream facing (DFP) or an Upstream Facing (UFP).
- DRQ - DMA Request
- DRTU - Intel: Diagnostics and Regulatory Testing Utility
- DSDT - The Differentiated System Descriptor Table, is generated by BIOS and necessary for ACPI. Implementation of ACPI in coreboot needs to be done in a “cleanroom” development process and MAY NOT BE COPIED from an existing firmware to avoid legal issues.
- DSC - Digital Signal Controller
- DSL - Digital subscriber line
- DSP - Digital Signal Processor
- DTB - U-Boot: Device Tree Binary
- dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip, vs Integrated TPMs or fTPMs (Firmware TPMs).
- DTS - U-Boot: Device Tree Source
- DUT - Device Under Test
- DVFS - ARM: Dynamic Voltage and Frequency Scaling
- DVI - Digital Video Interface
- DVT - Production Timeline: Design Validation Test
- DW - DesignWare: A portfolio of silicon IP blocks for sale by the Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA, I2c, memory controllers and more.
- DXE - UEFI: Driver Execution Environment
- DXIO - AMD: Distributed CrossBar I/O
- EBDA - Extended BIOS Data Area
- EBG - Intel: Emmitsburg PCH
- ECC - Error Correction Code - Typically used to refer to a type of memory that can detect and correct memory errors.
- EDID - Extended Display Identification Data
- edk2 - EFI Development Kit 2
- EDO - Memory: Extended Data
- A DRAM standard introduced in 1994 that improved upon, but was backwards compatible with FPM (Fast Page Mode) memory.
- eDP - Embedded DisplayPort
- EDS - Intel: External Design Specification
- EEPROM - Electrically Erasable Programmable ROM (common mistake: electrical erasable programmable ROM).
- EFI - Extensible Firmware Interface
- EFS - AMD: Embedded Firmware Structure: The data structure that AMD processors look for first in the boot ROM to start the boot process.
- EHCI - Enhanced Host Controller Interface - USB 2.0
- EHL - Intel: Elkhart Lake
- EIDE - Enhanced Integrated Drive Electronics
- EMI - ElectroMagnetic Interference
- eMMC - embedded MultiMedia Card
- EOP - End of POST
- EOL - End of Life
- EPP - Intel: Energy-Performance Preference
- EPROM - Erasable Programmable Read-Only Memory
- ESD - Electrostatic discharge
- eSPI - Enhanced System Peripheral Interface
- EVT - Production Timeline: Engineering Validation Test
- FADT - ACPI Table: Fixed ACPI Description Table
- FAE - Field Application Engineer
- FAT - File Allocation Table
- FCH - AMD: Firmware Control Hub
- FCS - Production Timeline: First Customer Shipment
- FDD - Floppy Disk Drive
- FFS - UEFI: Firmware File System
- FIFO - First In, First Out
- FIT - Intel: Firmware Interface Table
- FIT - Flattened-Image Tree
- FIVR - Intel: Fully Integrated Voltage Regulators
- Flashing - Flashing means the writing of flash memory. The BIOS on modern mainboards is stored in a NOR flash EEPROM chip.
- Flat mode - Real mode running in a way that allows it to access the entire 4GiB of the 32-bit address space. Also known as Unreal mode or Big Real mode
- FMAP - coreboot: Flash map
- FPDT - ACPI: Firmware Performance Data Table
- FPGA - Field-Programmable Gate Array
- Framebuffer - The
framebuffer is a part
of RAM in a computer which is allocated to hold the graphics
information for one frame or picture. This information typically
consists of color values for every pixel on the screen. A framebuffer
- Off-screen, meaning that writes to the framebuffer don’t appear on the visible screen.
- On-screen, meaning that the framebuffer is directly coupled to the visible display.
- FPM - Memory: Fast Page Mode - A DRAM standard introduced in 1990.
- FPU - Floating-Point Unit
- FSB - Front-Side Bus
- FSP - Intel: Firmware Support Package
- FSR - Intel: Firmware Status Register
- FTP - Network Protocol: File Transfer Protocol
- fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is based in firmware instead of actual hardware. It typically runs in some sort of TEE (Trusted Execution Environment).
- G0 - ACPI Global Power State: System is running
- G0-G3 - ACPI Global Power States
- G1 - ACPI Global Power State: System is suspended
- G2 - ACPI Global Power State: Soft power-off. The mainboard is off, but can be woken up electronically, by a button, wake-on-lan, a keypress, or some other method.
- G3 - ACPI Global Power State: Mechanical Off. There is no power going to the system except for a small battery to keep the CMOS contents, Real Time Clock, and maybe a few other registers running.
- GART - AMD: Graphics Address Remapping Table
- GATT - Graphics Aperture Translation Table
- GDT - Global Descriptor Table
- GLK - Intel: Gemini Lake
- GMA - Intel: Graphics Media Accelerator
- GNB - Graphics NorthBridge
- GNVS - Global Non-Volatile Storage
- GPD - PCH GPIO in Deep Sleep well (D5 power)
- GPE - ACPI: General Purpose Event
- GPI - GPIOs: GPIO Input
- GPIO - General Purpose Input/Output (Pin)
- GPMR - Intel: General Purpose Memory Range
- GPO - GPIOs: GPIO Output
- GPP - AMD: General Purpose (PCI/PCIe) port
- GPP - Intel: PCH GPIO in Primary Well (S0 power only)
- GPS - Nvidia: GPU Performance Scale
- GPT - UEFI: GUID Partition Table
- GPU - Graphics Processing Unit
- GSoC - Google Summer of Code
- GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
- GSPI - Generic SPI - These are SPI controllers available for general use, not dedicated to flash, for example.
- GUID - UEFI: Globally Unique IDentifier
- HDA - High Definition Audio
- HDCP - High-bandwidth Digital Content Protection
- HDD - Hard Disk Drive
- HDMI - High-Definition Multimedia Interface
- HDR - High Dynamic Range
- HECI - Intel: Host Embedded Controller Interface (Replaced by MEI)
- HID - Human Interface Device
- HOB - UEFI: Hand-Off Block
- HPD - Hot-Plug Detect
- HPET - High Precision Event Timer
- HSP - AMD: Hardware Security Processor
- HSTI - Hardware Security Test Interface
- HSW - Intel: Haswell
- Hybrid S3 - System Power State: This is where the operating system saves the contents of RAM out to the Hard drive, as if preparing to go to S4, but then goes into suspend to RAM. This allows the system to resume quickly from S3 if the system stays powered, and resume from the disk if power is lost.
- Hypertransport - AMD: The Hypertransport bus is an older (2001-2017) high-speed electrical interconnection protocol specification between CPU, Memory, and (occasionally) peripheral devices. This was originally called the Lightning Data Transport (LDT), which could be seen reflected in various register names. Hypertransport was replaced by AMD’s Infinity Fabric (IF) on AMD’s Zen processors.
I$ - Instruction Cache
I2C - Inter-Integrated Circuit is a bidirectional 2-wire bus for communication generally between different ICs on a circuit board.
I2S - Inter-IC Sound
I3C - I3c is not an acronym - The follower to I2C (Inter-Integrated Circuit)
- Also known as SenseWire
IA - Intel Architecture
IA-64 - Intel Itanium 64-bit architecture
IBB – Initial Boot Block
IBV - Independent BIOS Vendor
IC - Integrated Circuit
ICL - Intel: Ice Lake
IDE - Software: Integrated Development Environment
IDE - Integrated Drive Electronics - A type of hard drive - Used interchangeable with ATA, though IDE describes the drive, and ATA describes the interface. Generally replaced by SATA (Though again, SATA describes the interface, not actually the drive)
IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different slots.
IF - AMD: Infinity Fabric is a superset of AMD’s earlier Hypertransport interconnect.
IFD - Intel: Intel Flash Descriptor
IMC - AMD: Integrated micro-controller - An 8051 microcontroller built into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips. This never worked well for anything beyond fan control and caused numerous issues by reading from the BIOS flash chip, preventing other devices from communicating with the flash chip at runtime.
IMC - Integrated Memory Controller - This is a less usual use of the IMC acronym, but seems to be growing somewhat.
IO or I/O - Input/Output
IoC - Security: Indicator of Compromise
IOC - Intel: I/O Cache
IOE - Intel: I/O Expander
IOM - Intel: I/O Manager
IOMMU - I/O Memory Management Unit
IOMUX - AMD: The I/O Mux block controls how each GPIO is configured.
IOSF - Intel: Intel On-chip System Fabric
IP - Intellectual Property
IP - Internet Protocol
IPC - Inter-Processor Communication/Inter-Process Communication
IPI - Inter Processor Interrupt
IPMI - Intelligent Platform Management Interface
IRQ - Interrupt Request
ISA - Instruction set architecture
ISA (bus) - Industry standard architecture - Replaced generally by PCI (Peripheral Control Interface)
ISDN - Integrated Services Digital Network
ISH - AMD PSP: Image Slot Header
ISH - Intel: Integrated Sensor Hub - A microcontroller built into the processor to help offload data processing from various sensors on a mainboard.
ISP - Internet Service Provider
IVHD - ACPI: I/O Virtualization Hardware Definition
IVMD - ACPI: I/O Virtualization Memory Definition
IVRS - I/O Virtualization Reporting Structure
IWYU - Include What you Use - A tool to help with include file use
- JEDEC - Joint Electron Device Engineering Council
- JSL - Intel: Jasper Lake
- JTAG - The Joint Test Action Group created a standard for communicating between chips to verify and test ICs and PCB designs. The standard was named after the group, and has become a standard method of accessing special debug functions on a chip allowing for hardware-level debug of both the hardware and software.
- KBL - Intel: Kaby Lake
- KVM - Keyboard Video Mouse
- L0s - ASPM Power State: Turn off power for one direction of the PCIe serial link.
- L1-Cache - The fastest but smallest memory cache on a processor. Frequently split into Instruction and Data caches (I-Cache / D-Cache, also occasionally abbreviated as i$ and d$)
- L1 - ASPM Power State: The L1 power state shuts the PCIe link off completely until triggered to resume by the CLKREQ# signal.
- L2-Cache - The second level of memory cache on a processor, this is a larger cache than L1, but takes longer to access. Typically checked only after data has not been found in the L1-cache.
- L3-Cache - The Third, and typically final memory cache level on a processor. The L3 cache is typically quite a bit larger than the L1 & L2 caches, but again takes longer to access, though it’s still much faster than reading memory. The L3 cache is frequently shared between multiple cores on a modern CPU.
- LAN - Local Area Network
- LAPIC - Local APIC
- LBA - Logical Block Address
- LCD - Liquid Crystal Display
- LCAP - PCIe: Link Capabilities
- LED - Light Emitting Diode
- LF - Line Feed - The standard Unix EOL (End-of-Line) marker.
- LGTM - Looks Good To Me
- LLC - Last Level Cache
- LLVM - Initially stood for Low Level Virtual Machine, but now is just the name of the project, as it has expanded past its original goal.
- LP5 - LPDDR5
- LPDDR5 - Low-Power DDR 5 SDRAM
- LPC - The Low Pin count bus was a replacement for the ISA bus, created by serializing a number of parallel signals to get rid of those connections.
- LPM - USB: Link Power Management
- LPT - Line Print Terminal, Local Print Terminal, or Line Printer. - The Parallel Port
- LRU - Least Recently Used - a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
- LSB - Least Significant Bit
- LTE - Telecommunication: Long-Term Evolution
- LVDS - Low-Voltage Differential Signaling
- M.2 - An interface specification for small peripheral cards.
- MAC Address - Media Access Control Address
- MAFS - (eSPI) Master Attached Flash Sharing: Flash components are attached to the controller device and may be accessed by by the peripheral devices through the eSPI flash access channel.
- MBP - Intel UEFI: ME-to-BIOS Payload
- MBR - Master Boot Record
- MCA - Machine Check Architecture
- MCR - Machine Check Registers
- MCU - Memory Control Unit
- MCU - MicroController Unit
- MCTP - Management Component Transport Protocol
- MDFIO - Intel: Multi-Die Fabric IO
- MDN - AMD: Mendocino
- ME - Intel: Management Engine
- MEI - Intel: ME Interface (Previously known as HECI)
- Memory training - the process of finding the best speeds, voltages, and delays for system memory.
- MHU: ARM: Message Handling Unit
- MIPI: The Mobile Industry Processor Interface Alliance has developed a number of different specifications for mobile devices. The Camera Serial Interface (CSI) is a widely used interface that has made its way into laptops.
- MIPS - Millions of Instructions per Second
- MIPS (processor) - Microprocessor without Interlocked Pipelined Stages.
- MKBP - Matrix Keyboard Protocol
- MMC - MultiMedia Card
- MMIO - Memory Mapped I/O allows peripherals’ memory or registers to be accessed directly through the memory bus. When the memory bus size was very small, this was initially done by hiding any memory at that address, effectively wasting that memory. In modern systems, that memory is typically moved to the end of the physical memory space, freeing a ‘hole’ to map devices into.
- MMU - Memory Management Unit
- MMX - Officially, not an acronym, trademarked by Intel. Unofficially, Matrix Math eXtension.
- MODEM - Modulator-Demodulator
- Modern Standby - Microsoft’s name for the S0iX states
- MOP - Macro-Operation
- MOS - Metal-Oxide-Silicon
- MP - Production Timeline: Mass Production
- MPU - Memory Protection Unit
- MPTable - The Intel MultiProcessor specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. Version 1.1 of the spec was released in 1994, and the 1.4 version was released in 1995. This has been generally superseded by the ACPI tables.
- MRC - Intel: Memory Reference Code
- MSB - Most Significant Bit
- MSI - Message Signaled Interrupt
- MSR - Machine-Specific Register
- MT/s - MegaTransfers per second
- MTL - Intel: Meteor Lake
- MTL - ARM: MHU Transport Layer
- MTRR - Memory Type and Range Register
allows to set the cache behaviour on memory access in x86. Basically,
it tells the CPU how to cache certain ranges of memory
(e.g. write-through, write-combining, write-back…). Memory ranges
are specified over physical address ranges. In Linux, they are visible
/proc/mtrrand they can be modified there. For further information, see the Linux documentation.
- Nack - Negative Acknowledgement
- NB - North Bridge
- NBCI - Nvidia: NoteBook Common Interface
- NC - GPIOs: No Connect
- NDA - Non-Disclosure Agreement.
- NF - GPIOs: Native Function - GPIOs frequently have multiple different functions, one of which is defined as the default, or Native function.
- NFC - Near Field Communication
- NGFF - Next Generation Form Factor - The original name for M.2
- NHLT - ACPI Table - Non-HDA Link Table
- NIC - Network Interface Card
- NMI - Non-maskable interrupt
- Nonce - Cryptography: Number used once
- NOP - No Operation
- NTFS - New Technology File System
- NVME - Non-Volatile Memory Express - An SSD interface that allows access to the flash memory through a PCIe bus.
- NVPCF - Nvidia Platform and Control Framework
- NX - No Execute
- ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state
- ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state.
- ODM - Original Design Manufacturer
- OEM - Original Equipment Manufacturer
- OHCI - Open Host Controller
- non-proprietary USB Host controller for USB 1.1 (May also refer to the open host controller for IEEE 1394, but this is less common).
- OOBE - Out Of the Box Experience
- OPP - ARM: Operating Performance Points
- OS - Operating System
- OTA - Over the Air
- OTP - One Time Programmable
- PAE - physical address extension
- PAL - Programmable Array Logic
- PAM - Intel: Programmable Attribute Map - This is the legacy BIOS region from 0xC_0000 to 0xF_FFFF
- PAT - Page Attribute Table This can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR. Compared to MTRR, which sets memory types by physical address ranges, PAT sets them at Page level.
- PAT - Intel: Performance Acceleration Technology
- PATA - Parallel Advanced Technology Attachment - A renaming of ATA after SATA became the standard.
- PAVP - Intel: Protected Audio-Video Path
- PC - Personal Computer
- PC AT - Personal Computer Advanced Technology
- PC100 - An SDRAM specification for a 100MHz memory bus.
- PCB - Printed Circuit Board
- PCD - UEFI: Platform Configuration Database
- PCH - Intel: Platform Controller Hub
- PCI - Peripheral Control
- Replaced generally by PCIe (PCI Express)
- PCI Configuration Space - The PCI Config space is an address space for all PCI devices. Originally, this address space was accessed through an index/data pair by writing the address that you wanted to read/write into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC. This has been updated to an MMIO method which increases each PCI function’s configuration space from 256 bytes to 4K.
- PCIe - PCI Express
- PCMCIA: Personal Computer Memory Card International Association
- PCO - AMD: Picasso
- PCR: TPM: Platform Configuration Register
- PD - GPIOs: Pull-Down - Drives the pin to ground through a resistor. The resistor allows the pin to be set to the reference voltage as needed.
- PD - Power Delivery - This is a specification for communicating power needs and availability between two devices, typically over USB type C.
- PEG - PCIe Graphics - A (typically) x16 PCIe slot connected to the CPU for higher graphics bandwidth and lower latency.
- PEI - UEFI: Pre-EFI Initialization
- PEIM - UEFI: PEI Module
- PEP - Intel: Power Engine Plug-in
- PHX - AMD: Phoenix SoC
- PHY - PHYsical layer - The hardware that implements the send/receive functionality of a communication protocol.
- PI - Platform Initialization
- PIC - Programmable Interrupt Controller
- PII - Personally Identifiable Information
- PIO - Programmed I/O
- PIR - PCI Interrupt Router
- PIR Table - The PCI Interrupt Routing Table was a Microsoft specification that allowed windows to determine how each PCI slot was wired to the interrupt router.
- PIRQ - PCI IRQ
- PIT - Generally refers to the 8253/8254 Programmable Interval Timer.
- PLCC - Plastic leaded chip carrier
- PLL - Phase-Locked Loop
- PM - Platform Management
- PM - Power Management
- PMC Intel: Power Management Controller
- PMIC - Power Management IC (Pronounced “P-mick”)
- PMIO - Port-Mapped I/O
- PMU - Power Management Unit
- PNP - Plug aNd Play
- PoP - Point-of-Presence
- POR - Plan of Record
- POR - Power On Reset
- Port80 - The I/O port 0x80 is the address for BIOS writes to update diagnostic information during the boot process.
- POST - Power-On Self Test
- POTS - Plain Old Telephone Service
- PPI - UEFI: PEIM-to-PEIM Interface
- PPR - Processor Programming Reference
- PPT - AMD: Package Power Tracking
- PROM - Programmable Read Only Memory
- Proto - Production Timeline: The first initial production to test key concepts.
- PSE - Page Size Extention
- PSF - Intel: Primary Sideband Fabric
- PSP - AMD: Platform Security Processor
- PSPP - AMD: PCIE Speed Power Policy
- PTT - Intel: Platform Trust Technology - Intel’s firmware based TPM.
- PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a resistor. The resistor allows the signal to still be set to ground when needed.
- PVT - Production Timeline: (Production Validation Test
- PWM - Pulse Width Modulation
- PXE - Pre-boot Execution Environment
- QOS - Quality of Service
- RAID - redundant array of inexpensive disks - as opposed to SLED - single large expensive disk.
- RAM - Random Access Memory
- RAMID - Boards that have soldered-down memory (no DIMMs) can have various different sizes, speeds, and brands of memory chips attached. Because there is no SPD, (for cost savings) the memory needs to be identified in a different manner. The simplest of these is done using a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be used.
- RAPL - Running Average Power Limit
- RCS - Revision control system
- Real mode - The original 20-bit addressing mode of the 8086 & 8088 computers, allowing the system to access 1MiB of memory through a Segment:Offset index pair. In 2022, this is still the mode that x86-64 processors are in at the reset vector!
- RDMA - Remote Direct Memory Access is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
- RFC - Request for Comment
- RFI - Radio-Frequency Interference
- RGB - Red, Green, Blue
- RISC - Reduced Instruction Set Computer
- RMA - Return Merchandise Authorization
- RO - Read Only
- ROM - Read Only Memory
- RoT - Root of Trust
- RPL - Intel: Raptor Lake
- RRG - AMD (ATI): Register Reference Guide
- RSDP - Root System Description Pointer
- RTC - Real Time Clock
- RTD3 - Power State: Runtime D3
- RTFM - Read the Fucking Manual
- RTOS - Real-Time Operating System
- RVP - Intel: Reference Validation Platform
- RW - Read / Write
- RX - Receive
S-states - ACPI System Power States: Sleep states
S0 - ACPI System Power State: Fully running
S0 - S5 - ACPI System power states level 0 - 5, with each higher numbered power state being (theoretically) lower power than the previous, and (again theoretically) taking longer to get back to a fully running system than the previous.
S1 - ACPI System Power State: Standby - This isn’t use much anymore, but it used to put the Processor into a powered, but idle state, power down any drives, and turn off the display. This would wake up almost instantly because no processor context was lost in this state.
S2 - ACPI System Power State: Lower power than S1, Higher power than S3, I don’t know that this state was ever well defined by any group.
S3 - ACPI System Power State: Suspend to RAM - A low-power state where the processor context is copied to the system Memory, then the processor and all peripherals are powered off. On wake, or resume, the system starts to boot normally, then switches to restore the memory registers to the previous settings, restore the processor context from memory, and jump back to the operating system to pick up where it left off.
S4 - ACPI System Power State: Suspend to Disk. The processor context and all the contents of memory are copied to the hard drive. This is typically fully handled by the operating system, so resume is a normal boot through all of the firmware, then the OS restore the original contents of memory. Any critical processor state is restored.
S5 - ACPI System Power State: System is “completely powered off”, but still has power going to the board.
SAFS - (eSPI) Slave Attached Flash Sharing: Flash is attached to the peripheral device. Only valid for server platforms.
SAGV - Intel: System Agent Geyserville. The original internal name for the feature eventually released as Speedstep which controls the processor voltage and frequencies.
SAR - The Specific Absorption Rate is the measurement for the amount of Radio Frequency (RF) energy absorbed by the body in units of Watts per Kilogram. This may be built into coreboot as a table.
SAS - Serial Attached SCSI - A serialized version of SCSI used mostly for high performance hard drives and tape drives.
SATA - Serial Advanced Technology Attachment
SB - South Bridge
SB-RMI - AMD: Sideband Remote Management Interface
SB-TSI - SideBand Temperature Sensor Interface
SBA - SideBand Addressing
SBI - SideBand Interface
SBOM - Software Bill of Materials
SCI - System Control Interrupt
SCP - ARM: System Control Processor
SCP - Network Protocol: Secure Copy
SCSI - Small Computer System Interface - A high-bandwidth communication interface for peripherals. This is a very old interface that has seen numerous updates and is still used today, primarily in SAS (Serial Attached SCSI). The initial version is now often referred to as Parallel SCSI.
SD - Secure Digital card
SDHCI - SD Host Controller Interface
SDRAM - Synchronous DRAM
SDLE: AMD: Stardust Dynamic Load Emulator
SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only Memory)
SEV - AMD: Secure Encrypted Virtualization
SF - Snoop Filter
Shadow RAM - RAM which content is copied from ROM residing at the same address for speedup purposes.
Shim - A small piece of code whose only purpose is to act as an interface to load another piece of code.
SIMD - Single Instruction, Multiple Data
SIMM - Single Inline Memory Module
SIPI - Startup Inter Processor Interrupt
SIO - Super I/O
SKL - Intel: SkyLake
SKU - Stock Keeping Unit
SMBIOS - System Management BIOS
SMBus - System Management Bus
SMI - System management interrupt
SMM - System management mode
SMN - AMD: System Management Network
SMRAM - System Management RAM
SMT - Simultaneous Multithreading
SMT - Surface Mount
SMT - Symmetric Multithreading
SNP - AMD: Secure Nested Paging
SMU - AMD: System Management Unit
SO-DIMM: Small Outline Dual In-Line Memory Module
SoC - System on a Chip
SPD - Serial Presence Detect
SPL - AMD: Security Patch Level
SPM - Mediatek: System Power Manager
SPMI - MIPI: System Power Management Interface
SPR - Sapphire Rapids
SRAM - Static Random Access Memory
SSD - Solid State Drive
SSDT - Secondary System Descriptor Table - ACPI table
SSE - Streaming SIMD Extensions
SSH - Network Protocol: Secure Shell
SSI - Server System Infrastructure
SSI-CEB - Physical board format: SSI Compact Electronics Bay
SSI-EEB - Physical board format: SSI Enterprise Electronics Bay is a wider version of ATX with different standoff placement.
SSI-MEB - Physical board format: SSI Midrange Electronics Bay
SSI-TEB - Physical board format: SSI Thin Electronics Bay
SSP - Speech Signal Processor
STAPM - AMD: Skin Temperature Aware Power Management
STB - AMD: Smart Trace Buffer
SuperIO - The Super I/O (SIO) device provides a system with any of a number of different peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any of a number of various other devices.
SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0
- TBT - Thunderbolt
- TBT - Intel: Turbo Boost Technology
- TCC - Intel: Thermal Control Circuit
- TCP - Transmission Control Protocol
- TCPC - Type C Port Controller
- TCSS - Intel: Type C SubSystem
- TDMA - Time-Division Multiple Access
- TDP - Thermal Design Power
- TEE - Trusted Execution Environment
- TFTP - Network Protocol: Trivial File Transfer Protocol
- TGL - Intel: Tigerlake
- THC - Touch Host Controller
- Ti50 - Google: The next generation GSC (Google Security chip) on ChromeOS devices after Cr50
- TLA - Techtronics Logic Analyzer
- TLA - Three Letter Acronym
- TLB - Translation Lookside Buffer
- TME - Intel: Total Memory Encryption
- TOCTOU - Time-Of-Check to Time-Of-Use
- TOLUM - Top of Low Usable Memory
- ToM - Top of Memory
- TPM - Trusted Platform Module
- TS - TimeStamp
- TSN - Time-Sensitive Networking
- TSC - Time Stamp Counter
- TSEG - TOM (Top of Memory) Segment
- TSR - Temperature Sensor
- TWAIN - Technology without an interesting name.
- TX - Transmit
- TXE - Intel: Trusted eXecution Engine
- UART - Universal asynchronous receiver-transmitter
- UC - UnCacheable. Memory type setting in MTRR/PAT.
- uCode - Microcode
- UDK - UEFI: UEFI Development Kit
- UDP - User Datagram Protocol
- UEFI - Unified Extensible Firmware Interface
- UFC - User Facing Camera
- UFP - USB: Upstream Facing Port
- UFS - Universal Flash storage
- UHCI - USB: Universal Host Controller
- Intel proprietary USB 1.x Host controller
- Unreal mode - Real mode running in a way that allows it to access the entire 4GiB of the 32-bit address space - Also known as Big real mode or Flat mode.
- UMA - Unified Memory Architecture
- UMI - AMD: Unified Media Interface
- UPD - Updatable Product Data
- UPS - Uninterruptible Power Supply
- USART - Universal Synchronous/Asynchronous Receiver/Transmitter
- USB - Universal Serial Bus
- VBIOS - Video BIOS
- VBNV - Vboot Non-Volatile storage
- VBT - Video BIOS Table
- VESA - Video Electronics Standards Association
- VGA: Video Graphics Array
- VID: Vendor Identifier
- VID: AMD: Voltage Identifier
- VLB - VESA Local Bus
- VOIP - Voice over IP
- Voodoo mode - a silly name for Big Real mode.
- VPD - Vital Product Data
- VPN - Virtual Private Network
- VR - Voltage Regulator
- VRAM - Video Random Access Memory
- VRM - Voltage Regulator Module
- VT-d - Intel: Virtualization Technology for Directed I/O
- WAN - Wide Area Network
- WB - Cache Policy: Write-Back
- WC - Cache Policy: Write-Combining
- WCAM - World-facing Camera - A camera on a device that is not intended to be used as a webcam, but instead to film scenes away from the user. For clamshell devices, his may be on the keyboard panel for devices devices that open 360 degrees, or on the outside of the cover. For tablets, it’s on the the side away from the screen.
- WDT - WatchDog Timer
- WFC - World Facing Camera
- WLAN - Wireless LAN (Local Area Network)
- WWAN - Telecommunication: Wireless WAN (Wide Area Network)
- WP - Cache policy: Write-Protected
- WO - Write-only
- WOL - Wake-on-LAN
- WT - Cache Policy: Write Through
- x64 - Another name for x86-64 or AMD64.
- x86 - x86 Originally referred to any device compatible with the 8088/8086 architectures, this now typically means compatibility with the 80386 32-bit instruction set (also referred to as IA-32)
- x86-64 - The 64-bit extension to the x86 architecture. Also known as AMD64 as it was developed by AMD. Long-mode refers to when the processor is running in the 64-bit mode.
- XBAR - AMD: Abbreviation for crossbar, their command packet switch which determines what data goes where within the processor or SoC
- XHCI - USB: Extensible Host Controller Interface - USB Host controller supporting 1.x, 2.0, and 3.x devices.
- ZIF - Zero Insertion Force