As no datasheet is available most of the functions have been reverse engineered and might be inaccurate or wrong.
|3||Com2 / IR|
|4||LED and PWR button CTRL|
|0x1e||SUSPEND CTL ?|
On most SuperIOs the use of LDN4 is forbidden. That’s not the case on NPCD378.
It exposes 16 byte of IO config space to control the front LEDs PWM duty cycle and power button behaviour on normal / during S3 resume.
A custom PS/2 AUX port.
Looks like a WDT.
The registers are accessible via IO space and are located at LDN8’s IOBASE.
|0x4||Host Write CTRL|
|0x10 - 0xfe||HWM Page #|
|0xff||Page index select|
Host Write CTRL¶
Bit 0 must be cleared prior to writing any of the HWM register and it must be set after writing to HWM register to signal the SuperIO that data has changed. Reading register is possible at any time and doesn’t need special locking.
The SuperIO exposes 16 different pages. Nearly all registers are unknown.
|0x98||PSU fan PWM|
The 4 LSB of the page index register selects which HWM page is active. A write takes effect immediately.