SiFive HiFive Unleashed¶
For general setup instructions, please refer to the Getting Started Guide.
The following things are still missing from this coreboot port:
- Support running romstage from flash (fix stack) to support boot mode 1
- Starting the U54 cores
- FU540 PIN configuration and GPIO access macros
- Provide serial number to payload (e.g. in device tree)
- Implement instruction emulation
- Support for booting Linux on RISC-V
- SMP support in trap handler
make menuconfig and select SiFive/HiFive Unleashed in the Mainboard
A total of 16 boot modes can be configured using the switches labeled
MSEL3. The most important ones are as follows:
- MSEL=1: Jump directly into the SPI flash, bypassing ROM1
- MSEL=11: Load FSBL from SD-card
- MSEL=15: Default boot mode; Load FSBL/coreboot from a GPT partition on SPI flash
The HiFive Unleashed has an 32 MiB SPI flash (ISSI IS25WP256D), that can be programmed from within Linux running on the board, via USB/JTAG, or directly with an SPI programmer.
The SPI flash can be accessed as
/dev/mtd0 from Linux.
To program the flash via USB/JTAG, connect the USB port to a computer. If the
board is powered on, two new serial ports, for example
/dev/ttyUSB1 will appear. The first is JTAG, and the second is connected to
the SoC’s UART.
- Download and build the RISC-V fork of OpenOCD.
- Download the OpenOCD script for Freedom Unleashed.
- Start OpenOCD with
openocd -f openocd.cfg
- Connect to OpenOCD’s command interface (via telnet) and enter the line
> flash write_image erase unlock build/coreboot.rom 0x20000000 auto erase enabled auto unlock enabled wrote 33554432 bytes from file build/coreboot.rom in 1524.943848s (21.488 KiB/s)
Note that programming the whole flash with OpenOCD isn’t fast. In this example it took just over 25 minutes. This process can be sped up considerably by building/flashing a smaller image; OpenOCD does not check if the image and the flash have the same size.
The zeroth-stage bootloader (ZSBL) in ROM1 can print error codes on the serial console in certain situations.
// Error codes are formatted as follows: // [63:60] [59:56] [55:0] // bootstage trap errorcode // If trap == 1, then errorcode is actually the mcause register with the // interrupt bit shifted to bit 55.
(— from the SiFive forum)